publications
Please find below information that may be of interest to the
press and media. At Plessey Semiconductors our engineers are committed to research and innovation. This long-standing committment is reflected in the number of scientific, peer-reviewed publications and patent applications our engineering and development teams have generated over the years.
Technology Development
M.C. Wilson, S. Nigrin et al
A modular approach to the manufacture of a high performance complementary Bipolar Technology Family
Proceeding of Semicon West 2004 , San Francisco, USA 13 July 2004
M.C. Wilson, P.Osborne et al
A 12 Volt , 12GHz Complementary Bipolar technology for High Frequency Analogue Application
Proceeding of the 32nd European Solid State Device Research Conference, Firenza, Italy 24-26 September 2002
S.Nigrin, P.Osborne et al
A complementary Bipolar Technology on SOI Technology 50GHz NPN and 35 GHz PNP devices.
2002 IEEE International SOI Conference October 7-10 Williamsburg Virginia , USA
M.C. Wilson, P. Osborne et al
A New High Performance Complementary Bipolar Technology Featuring 45GHz NPN and 20GHz PNP Devices
Proc. SPIE Microelectronic Manufacturing 1999, pp3881-10, Santa Clara, USA
M.C. Wilson, P. Osborne et al
Process HJ: A 30GHz NPN and 20 GHz PNP Complementary Bipolar Process for High Linearity RF Circuits
Proc. IEEE 1998 BCTM, pp164-167, Minneapolis, USA
M.C. Wilson, P. Osborne et al
A New Complementary Bipolar Process featuring a Very High Speed PNP
Proc. ESSDERC 1998, pp380-383, Bordeaux, France
B. Martin, N. Harper
Novel resist patterning strategies for the definition of high resolution via holes in polyimide interlayer dielectric.
Proc. Advances in Resist Technologies and Processing IX pp 586-596, SPIE 1992.
Measurement Technique Development
L. Tan, M. M. A. Hakim, S. Connor , A. Bousquet , W. Redman-White, P. Ashburn, S. Hall.
Characterisation of CMOS Compatible Vertical MOSFETs with New Architectures through EKV Parameter Extraction and RF Measurement
Presented at Ultimate Integration on Silicon (ULIS), Aachen, Germany, 2009
L. Tan, M. M. A. Hakim, S. Connor , A. Bousquet, W. Redman-White, P. Ashburn, S. Hall
Compact Model Extraction Issues of Nonstandard CMOS Compatible Vertical MOSFETs
Ultimate Integration on Silicon (ULIS), Glasgow, UK, 2010
S.D. Connor, S.J. Harrington, A.J. Manson, S. Nigrin, S. Thomas, M.C. Wilson
Automated On-Wafer Measurement of Noise Figure and Base Spreading Resistance
ICSICT 2004 Beijing China Oct 18-21 (7th International Conference on Solid State and Integrated Circuits Technology)
MMA Hakim, L. Tan, A Abuelgasim, K. Mallik, S. Connor, A Bousquet, C. H. de-Groot, W. Redman-White, S. Hall and P. Ashburn.
Self-aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications.’
Accepted in IEEE Trans. Electron. Dev. July 2010
S.D. Connor
Measurement of '1/f' Noise in Poly-silicon Emitter Bipolar Transistor Structures
Proceedings of IEEE International Conference on Microelectronic Test Structures, pp33-38, March 153-157, 1998.
S.D. Connor
On Wafer Noise Measurement Using Bipolar Transistor RF Test Structures
Proceedings of IEEE International Conference on Microelectronic Test Structures, pp43-48, March 17-20, 1997
S.D. Connor; D. Evanson
Automated Extraction of Matching Parameters for Bipolar Transistor Technologies
Proceedings of IEEE International Conference on Microelectronic Test Structures, pp33-38, March 25-28, 1996
FAB Management
N. Harper
SMIF and Mini-Environment Technology - The Reality
Future Fab International Volume 3, July 1997.
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